Winners 2017

Device Design and Packaging Award


Makers of flagship smartphones seek to squeeze the highest levels of functionality and performance into ultra-slim handsets. Because these high-end phones are designed for global or super-regional use they also need to integrate support for many different regional LTE bands as well as multiple carrier aggregation (CA band combinations.

The RF Fusion portfolio of solutions from Qorvo contains multiple high-performance modules focused on differentiated performance – achieved by integrating Qorvos leading technologies such as NoDrift and LowDrift filters along with advanced power amplifier (PA and switch technologies. All delivered in the industrys smallest form factors. Qorvo’s RF Fusion provides OEMs with a complete RF Front End (RFFE solution that incorporates all major transmit and receive functionality including support for major frequency bands into three compact modules covering the high-band mid-band and low-band regions of the spectrum. The architecture is also designed to integrate support for the rapid deployment of CA in markets worldwide.

 

Substrates & Materials Award

Element Six’s TM200 is the highest thermal conductivity bulk heat spreader material available in the market with room temperature thermal conductivity 2000 W/mK (more than 5x copper or 10x other commonly used ceramic materials. Element Six has developed specialized chemical vapor deposition (CVD processes to produce free standing diamond substrates that deliver this market leading thermal conductivity. Designed to enable extreme performance thermal packaging for use in high power or high power density devices TM200 enables increased power and reliability and reduced system size.

The spreading of heat within TM200 is highly isotropic spreading the heat with equal efficiency in a planar direction as well as through the material. It is produced in diameters up to 5 inches. A crucial element in developing any new disruptive technology is the control of the engineering of the basic building blocks.

Chemical vapor deposition (CVD grown diamond as a high performance heat spreader is considered an enabling material for a wide range of disruptive electronics from gallium nitride (GaN solid state RF X-band power amplifiers (PAs to advanced application-specific integrated circuits (ASICs to laser diodes. Understanding the engineering of the thermal properties of grown diamond is an essential part of any such building blocks. While there are CVD diamond growth chemistries that continue to promote re-nucleation to avoid grain size development for TM200’s thermal conductivity it is imperative to choose conditions producing excellent crystal quality consistent with:

• Exceptional intra grain purity with respect to point and extended defect
• Exceptionally well inter-grown and low defect density grain boundaries

Large grains augmented with significant levels of post synthesis processing the ultimate product delivers precision manufactured parts incorporated in a platform that delivers more than 2000 W/mK thermal conductivity with 10M12 Ω-cm bulk and 1010 Ω-cm surface resistivity at high volume.

 

High-volume Manufacturing Award


Last year Oxford Instruments announced the development of a SiC via plasma etch process using its PlasmaPro100 Polaris system.

SiC is becoming an increasingly important material, particularly for high performance GaN RF devices using SiC as a substrate. A smooth via etch through the SiC is essential to the functioning of these devices.

Capabilities of Oxford Instruments' SiC via process include high SiC etch rate enabling maximum throughput; smooth sidewalls for problem free post etch metallisation; and high selectivity to underlying GaN layer giving a smooth, low damage stop onto the GaN device layers.

Other features include clamping of sapphire carriers using Oxford Instruments' unique patented Electrostatic Clamp technology ensuring good sample temperature control and maximum yield; the capability of etching SiC and GaN in the same tool through advanced plasma source technology; and high utilisation provided by long Mean Time Between Cleans (MTBC).

 

Innovation Award


Scientists at IBM Research GmbH achieved the first demonstration of an InGaAs/SiGe CMOS technology on Si substrate using processes suitable for high-volume manufacturing on 300 mm wafers. InGaAs/SiGe hybrid integration is the main path to enable further improvement of power/performance trade off metrics for digital technologies beyond the 7 nm node. Based on selective epitaxy their approach yielded functional inverters and dense arrays of 6T-SRAMs the basic blocks of digital CMOS circuits.

This work – first of a kind – has been disclosed at the last VLSI Technology conference. It concludes a series of key demonstrations for InGaAs/SiGe CMOS reported in multiple contributions and highlights for the last four years at IEDM meetings and VLSI Technology Symposia. Since many years the technological bottleneck is to demonstrate a path that enable simultaneously the growth of defect-free InGaAs the fabrication of high performance InGaAs field effect transistors “on-insulator” and their co-processing with SiGe devices all on a silicon substrate.

A few approaches have been proposed but the work nominated is the only one that reports basic building blocks of digital circuits at relevant dimensions and achieves a major milestone towards a manufacturable hybrid InGaAs/SiGe CMOS technology. It features in a single technology the selective growth of high quality InGaAs-on-Insulator regions the fabrication of InGaAs finFETs with physical gate length Lg= 35 nm and good device characteristics and the processing of functional 6T-SRAM cells with a cell area ≈0.4mµ2. All metrics compare favourably to industrial state-of-the-art numbers (e.g. ≈0.1µm2 for an SRAM cells in 22 nm technology. It clearly highlights the potential of the nominated work as the method of choice to co-integrate InGaAs and SiGe MOSFETs for advanced CMOS technology. It also opens the door towards future low cost RF or photonic circuits based on a similar hybrid III-V silicon technologies.


Key Dates 2016/2017

Nominations open 25th November 2016
Nominations close 9th January 2017
Shortlist announced 16th January 2017
Voting opens 16th January 2017
Voting closes 21st February 2017
Winners informed 21st February 2017
Awards ceremony 7th March 2017

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